Digital-to-time converters, referred to as timing digital-to-analog converters (timing DACs), may be used to adjust timing of events in integrated circuits, for example. Timing DACs typically include circuits that provide coarse timing adjustments and fine timing adjustments, respectively, in order to obtain the desired timing adjustments.
FIGS. 1A and 1B are block diagrams illustrating known circuits for providing coarse timing adjustments. Generally, coarse timing adjustments are accomplished by switching delay elements, such as complementary metal-oxide-semiconductor (CMOS) gates, into or out of a delay path using multiplexers.
FIG. 1A is a block diagram depicting a known coarse timing DAC 101, which multiplexes between taps of a CMOS delay chain, including delay elements 111-113 and dummy load 114. However, a large number of taps requires use of a wide multiplexer or a multiplexer tree, shown by multiplexers 121-123, controllable by coarse adjustment control bit cAdj<0>, and multiplexer 130, controllable by coarse adjustment control bits cAdj<2:1>. The multiplexer tree adds non-trivial delay.
FIG. 1B is a block diagram depicting another known coarse timing DAC 102, having a trombone structure that uses delays of multiplexers 141-144 as part of the delay line, thus decreasing the minimum delay time. The delay of the coarse timing DAC 102 is determined in response to a binary coarse adjustment control word cAdj<1:0> and corresponding coarse select signals cSel3-cSel0. The coarse select signals cSel3-cSel0 may be one-hot coded, for example, which means that only one bit of the coarse select signals cSel3-cSel0 is set to “1” at a time, and the remaining bits of the coarse select signals cSel3-cSel0 are set to “0”, e.g., 0001, 0010, 0100, and 1000. A binary to one-hot decoder 145 converts the binary coarse adjustment control word cAdj<1:0> to one-hot coded coarse select signals cSel3-cSel0. The coarse select signals cSel3-cSel0 determine the number of multiplexers 141-144 that input signal In traverses before it arrives at the output Out. Whichever coarse select signal cSelN that is set to “1” forces the corresponding multiplexer 141-144 to select the input signal In. For example, Table 1 shows the multiplexers traversed by the input signal In in response to a binary coarse adjustment control word and corresponding coarse select signals cSel3-cSel0.
TABLE 1Binary coarseadjustmentMultiplexersDecimalcontrol wordCoarse select signalstraversed bynumbercAdj<1:0>cSel3 . . . cSel0input signal In00000011411010010142→1412100100143→142→1413111000144→143→142→141
The coarse timing DAC 102 effectively limits the size of the delay time steps to the relatively large delay of a 2:1 multiplexer. In comparison, the coarse timing DAC 101 of FIG. 1A can be designed with delay time steps of two inverter delays (for a single-ended delay chain) or even one inverter delay (for a pseudo-differential delay chain).
FIGS. 2A and 2B are block diagrams illustrating known circuits for providing fine timing adjustments. FIG. 2A is a block diagram depicting known fine timing DAC 201, including delay elements 211 and 212, which may be CMOS inverters, for example. A variable load capacitor 213 is connected from a node between the delay elements 211 and 212 to ground. Thus, the fine timing DAC 201 adjusts time delay by varying the load capacitor 213 of the delay element 211.
FIG. 2B is a block diagram depicting another known fine timing DAC 202, which includes interpolator 250 and delay element 261. The interpolator 250 includes multiplexers 251-253. Each of the multiplexers 251-253 receives the input signal In directly and delayed signal D via delay element 261 in order to blend them according to a variable ratio between the two signals, determined in response to fine adjustment control word fAdj.
In applications requiring a wide range of time adjustment, as well as fine step size, a coarse timing DAC (e.g., shown in FIG. 1A or 1B) and a fine timing DAC (e.g., shown in FIG. 2A or 2B) may be cascaded to form a timing DAC, in which the range of the fine timing adjustment covers at least a LSB of the coarse timing adjustment circuit to avoid dead zones. However, cascading coarse and fine timing DACs is problematic when minimum delay time is critical because the minimum delay time of the resulting timing DAC is the sum of the respective minimum delay times of the coarse and fine timing DACs. Using a multiplexer tree-based structure, such as that shown in FIG. 1A, aggravates the problem because the structure has a large minimum delay time itself. Also, the relatively large LSB of a trombone structure, such as that shown in FIG. 1B, makes it difficult to the design a fine timing adjustment circuit with a sufficiently wide range.